VHDL bit rotation function syntax error? -

VHDL bit rotation function syntax error? -

i doing school work i'm making own rolling/shifting function. below code wrote, when seek compile syntax error on rownum<=rol(rowcount,1);

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; architecture main of proj function "rol" (a: std_logic_vector; n : natural) homecoming std_logic_vector begin homecoming std_logic_vector(unsigned(a) rol n); end function; signal rownum : std_logic_vector(2 downto 0); signal rowcount : std_logic_vector(2 downto 0); begin process begin wait until rising_edge(i_clock); **rownum<=rol(rowcount,1);** end process; end architecture main;

there couple of things need addressed here.

firstly, need entity statement:

entity proj port( i_clock : in std_logic ); end proj;

this declares signals inputs , outputs entity. in case, it's clock. can add together rownum , rowcount inputs , outputs needed.

your function name shouldn't in inverted commas, , overloading existing operator isn't thought either.

function rol_custom (a: std_logic_vector; n : natural) homecoming std_logic_vector begin homecoming std_logic_vector(unsigned(a) rol n); end function;

here's synthesizable code:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity proj port( i_clock : in std_logic ); end proj; architecture main of proj function rol_custom (a: std_logic_vector; n : natural) homecoming std_logic_vector begin homecoming std_logic_vector(unsigned(a) rol n); end function; signal rownum : std_logic_vector(2 downto 0); signal rowcount : std_logic_vector(2 downto 0); begin process begin wait until rising_edge(i_clock); rownum<=rol_custom(rowcount,1); end process; end architecture main;

however, though should synthesize, results won't create sense, because rowcount has not been given value. in order define it, might want add together process drives signal based on criteria (a counter?) or add together input in entity definition.

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