type conversion can not have aggregate operand (error in modelsim) -

type conversion can not have aggregate operand (error in modelsim) -

i'm novice vhdl. i'm getting next errors while compiling in modelsim6.5b

type conversion(to g) cannot have aggregate operand, no feasible entries infix operator "and", target type ieee.std_logic_1164.std_ulogic in variable assignment different - look type std.stadard.integer

any help on these , reason behind helpful.

this bundle i've written

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.std_logic_unsigned.all; bundle enc_pkg constant n : integer := 1; constant k : integer := 2; constant m : integer := 3; constant l_total : integer := 10; constant l_info : integer := 10; type t_g array (1 downto 1, 3 downto 1)of std_logic; signal g:t_g; type array3_10 array (3 downto 1, 10 downto 0) of std_logic; type array2_10 array (2 downto 1, 10 downto 0) of std_logic; procedure rsc_encoder( x : in std_logic_vector(1 10); terminated : in std_logic; y : out array2_10); procedure encode_bit(input : in std_logic; state_in : in std_logic_vector(1 2); output : out std_logic_vector(1 2); state_out : out std_logic_vector(1 2)); procedure encoderm (infor_bit : in std_logic_vector(1 8); en_output : out std_logic_vector(1 20)); end enc_pkg; bundle body enc_pkg procedure rsc_encoder( x : in std_logic_vector(1 10); terminated : in std_logic; y : out array2_10)is variable state : std_logic_vector(1 2); variable d_k : std_logic; variable a_k : std_logic; variable output_bit : std_logic_vector(1 2); variable state_out : std_logic_vector(1 2); begin in 1 m loop state(i) := '0'; end loop; in 1 l_total loop if(terminated = '0' or (terminated = '1' , <= l_info)) d_k := x(i); elsif(terminated = '1' , > l_info)then d_k := (g(1, 2) , state(1)) xor (g(1, 3) , state(2)); end if; a_k := (g(1, 1) , d_k) xor (g(1, 2) , state(1)) xor (g(1, 3)) , state(2)); encode_bit(a_k, state, output_bit, state_out); state := state_out; output_bit(1) := d_k; y(1, i) := output_bit(1); y(2, i) := output_bit(2); end loop; end rsc_encoder; procedure encode_bit(input : in std_logic; state_in : in std_logic_vector(1 2); output : out std_logic_vector(1 2); state_out : out std_logic_vector(1 2))is variable temp : std_logic_vector(1 2); begin in 1 n loop temp(i) := g(i, 1) , input; j in 2 k loop temp(i) := temp(i) xor (g(i, j) , state_in(j-1)); end loop; end loop; output := temp; state_out := input & state_in(m-1); end encode_bit; procedure encoderm (infor_bit : in std_logic_vector(1 8); en_output : out std_logic_vector(1 20))is --type array2_10 array (2 downto 1, 10 downto 0) of integer; --type array3_10 array (3 downto 1, 10 downto 0) of integer; variable interleaved : std_logic_vector(1 10); variable input : std_logic_vector(1 10); variable puncture : std_logic; variable output : array3_10; variable y : array2_10; variable en_temp : std_logic_vector(1 10); begin input := "0000000000"; in 1 8 loop input(i) := infor_bit(i); end loop; rsc_encoder(input, terminated 1, y); in 1 10 loop output(1, i) := y(1, i); output(2, i) := y(2, i); end loop; interleaved(1) := output(1, 1); interleaved(2) := output(1, 4); interleaved(3) := output(1, 7); interleaved(4) := output(1, 10); interleaved(5) := output(1, 2); interleaved(6) := output(1, 5); interleaved(7) := output(1, 8); interleaved(8) := output(1, 3); interleaved(9) := output(1, 6); interleaved(10) := output(1, 9); rsc_encoder(interleaved, terminated 0, y); in 1 10 loop output(3, i) := y(2, i); end loop; if puncture = '1'then in 1 10 loop j in 1 3 loop en_output(3*(i-1)+j) := output(j, i); end loop; end loop; elsif puncture = '0' in 1 l_total loop en_temp(n*(i-1)+1) := output(1, i); if((i rem 2) = 1)then en_temp(n*i) := output(2, i); else en_temp(n*i) := output(3, i); end if; end loop; end if; en_output := en_temp; end encoderm; end enc_pkg;

let's take little portion of code:

type g array (1 downto 1, 3 downto 1)of integer;

...

variable state : std_logic_vector(1 2);

...

a_k := (g(1, 1) , d_k) xor (g(1, 2) , state(1)) xor (g(1, 3)) , state(2));

two things:

types

g type, not signal...

do this. first define new type in vhdl. create (let's talk c now) 'variable' of new created type. on (again, let's talk c) 'variable', stuff.

type t_g array (1 downto 1, 3 downto 1)of integer; signal g: t_g; operators

g(1,2) integer, state(1) std_logic. there no and operator these 2 types combined. need this:

if state(1) = '1' .... else .... end if;

compiler-errors type-conversion vhdl