system verilog - SystemVerilog vs C++ assignment: reference or copy? -

system verilog - SystemVerilog vs C++ assignment: reference or copy? -

i have c++ background. tracking downwards bug in systemverilog code working on , surprised find thought object-copying assignment reference assignment. simplified code shows mean:

for (int = 0; < max_num; ++i) { var cls_obj obj1; obj1 = obj_array[i]; some_function(obj1); // modifies object passed in // @ point both obj1 , obj_array[i] modified. // other code goes here }

i expecting obj1 modified. because of var keyword? how re-create assignment vs. reference assignment work in systemverilog? having hard time finding info web searches.

class variables in systemverilog references, or handles. instances created when utilize new keyword.

so in example, obj1 , obj_array[i] both refer (or point) same instance.

by default, function parameters in systemverilog passed value. class handles treated values, class pass function passed reference.

there built-in mechanism in language shallow re-create when initializing class object.

packet p1; packet p2; p1 = new; p2 = new p1;

this shallow copy. objects handles copied!

this explained examples in chapter 8.11 of ieee 1800-2009.

the var keyword not have behavior seeing. in fact, i've never seen or used var. according lrm allows 1 omit type when declaring variable. in code, type (cls_obj) specified don't think presence doing thing.

system-verilog