verilog - Illegal reference Error -

verilog - Illegal reference Error -

i writing ripple counter using d-flip flops. next code giving me illegal reference error within initial block q2,q3,q4variables. why that?

module rcounter; reg d,d2,d3,d4,clk; wire q,q2,q3,q4; dflipflop a(d,q,clk); dflipflop a1(d2,q2,q); dflipflop a2(d3,q3,q2); dflipflop a3(d4,q4,q3); initial begin clk =1; d=0;d2=0;d3=0;d4=0;q2=0;q3=0;q4=0; #2 d=1;d2=~q2; d3=~q3; d4=~q4; #2 d=0;d2=~q2; d3=~q3; d4=~q4; #2 d=1;d2=~q2; d3=~q3; d4=~q4; #2 d=0;d2=~q2; d3=~q3; d4=~q4; #2 d=1;d2=~q2; d3=~q3; d4=~q4; #2 d=0;d2=~q2; d3=~q3; d4=~q4; #2 d=1;d2=~q2; d3=~q3; d4=~q4; end begin #2 assign clk = ~ clk; end endmodule

d flipflop module:

module dflipflop(d,q,clk); input d,clk; output q; assign q = clk?( (d==1)? 1:0) : q; endmodule

how can solve problem?

regards

as vlad lazarenko has pointed out can not assign values wires within initial or always@ blocks.

the prepare alter type wire reg.

or declare (except tristate buses) logic if using systemverilog.

the definition of reg or wire applies level of hierarchy. reg can drive port treated wire within module.

reg not imply flip-flop or register simulator optimisation.

it worth noting flip-flop instantiated via:

reg x; @(posedge clk or negedge rst_n) begin if(~rst_n) begin //reset status x <= 1'b0; end else begin x <= next_value; end end

reference verilog hdl